A fault-tolerant hardening-by-design frequency divider has been proposed for clock and data recovery in a 28-nm CMOS process. By means of the mandatory updating mechanism. the proposed divider can update the state of the D flip-flops from an error state to a correct state so as to avoid single-event transient (SET) accumulation in different finite-state machines (FSMs). Our proposed d... https://steedaes.shop/product-category/exhaust/